This invention relates to time synchronization over a network.
A network generally includes elements that may need to coordinate their operations. When coordination is required, some of these elements have internal clocks that are synchronized with a master clock. One technique for synchronizing is to periodically send messages from the master clock to the network elements. These messages include a time value that the master clock provides (i.e., a time stamp). An element receiving one of the messages estimates the master clock time by calculating any delay between the time the master clocks stamps the message and when the element processes the message and by adding the calculated delay to the time stamp of the message. The element then can adjust, i.e., synchronize, its internal clock to match the estimated time of the master clock. The mentioned delay is often referred to as latency.
One source of latency is the time it takes for the message to travel from the master clock to the element. One way for an element to calculate this travel time is to send a message on a round trip to the master clock and then measure the time it takes the message to return. The element then splits the round trip time to calculate the time it takes for the message to travel from the master clock to the element.
There are usually thresholds beyond which adjustments to the internal clock of an element being considered may not improve synchronization with the master clock. One such threshold is a margin of error with which a network element can estimate the time of the master clock. The described latency is a significant contributor to this margin of error. Conventional synchronization schemes define a preset set value of latency beyond which the margin of error will be too great to synchronize. An element will thus discard a time synchronization message having latency that is greater than the preset value.
Another threshold is a maximum which a network element can change its internal clock without breaking the network. In this case, the element is able to accurately estimate the time of the master clock but the element's internal clock is so much out of synch with the master clock that adjustment will result in errors in the network. Conventional synchronization schemes also define a preset value for this threshold of maximum adjustment.